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參數資料
| 型號： | UCC3913J |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 6/9頁 |
| 文件大小： | 158K |
| 代理商： | UCC3913J |
6
UCC1913
UCC2913
UCC3913
1
μ
A R
V
FET
PL
Therefore, the maximum average power dissipation in
the MOSFET can be approximated by:
P
FET avg
(
1
μ
V
IMAX
A R
V
FET
IMAX
A R
μ
FET
PL
PL
)
=
=
1
Notice that in the approximation, V
FET
cancels. therefore,
average power dissipation is limited in the NMOS pass
element.
Overload Comparator
The linear amplifier in the UCC1913 ensures that the
output NMOS does not pass more than I
MAX
(which is
V
IMAX/
R
S
). In the event the output current exceeds the
programmed I
MAX
by 0.2V/R
S
, which can only occur if
the output FET is not responding to a command from the
IC, the CT pin will begin charging with I3, 1mA, and con-
tinue to charge to approximately 8V. This allows a con-
stant fault to show up on the SD/FLT pin, and also since
the voltage on CT will only charge past 2.5V in an over-
load fault mode, it can be used for detection of output
FET failure or to build in redundancy in the system.
Determining External Component Values
Referring now to Figure 3. To set R
VDD
the following
must be achieved:
V
R
R
R
VDD
+
1
2
(
)
(
)
V
mA
2
IN
min
>
+
10
In order to estimate the minimum timing capacitor, C
T
,
several things must be taken into account. For example,
given the schematic below as a possible (and at this
point, a standard) application, certain external compo-
nent values must be known in order to estimate C
T(min)
.
Now, given the values of C
OUT
, Load, R
SENSE
, VSS, and
the resistors determining the voltage on the IMAX pin,
the user can calculate the approximate startup time of
the node V
OUT
. This startup time must be faster than the
time it takes for CT to charge to 2.5V (relative to VSS),
and is the basis for estimating the minimum value of CT.
In order to determine the value of the sense resistor,
R
SENSE
, assuming the user has determined the fault cur-
rent, R
SENSE
can be calculated by:
mV
I
FAULT
R
SENSE
=
50
APPLICATION INFORMATION (cont.)
Figure 3.
∞
Figure 4. Plot average power vs. FET voltage for
increasing values of R
PL
.
SHUTDOWN
FAULT OUT
SD/FLT
7
R4
R3
VSS
LEVEL SHIFT
LOCAL VDD
LOCAL GND
Figure 5. Possible level shift circuitry to interface to
the UCC1913.
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