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參數資料
| 型號： | UDA1320ATS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Low-Cost Stereo Filter DAC(低價格立體聲濾波數模轉換器) |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 102K |
| 代理商： | UDA1320ATS |
2000 Jan 10
14
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
15.2
Digital
V
DDD
= V
DDA
= 2.7 to 3.6 V; T
amb
=
20 to +85
°
C; R
L
= 5 k
.
All voltages referenced to ground (pins 5 and 15); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
T
sys
system clock cycle
f
sys
= 256f
s
f
sys
= 384f
s
f
sys
= 512f
s
f
sys
< 19.2 MHz
f
sys
≥
19.2 MHz
f
sys
< 19.2 MHz
f
sys
≥
19.2 MHz
78
52
39
30
40
30
40
88
59
44
244
162
122
70
60
70
60
ns
ns
ns
%T
sys
%T
sys
%T
sys
%T
sys
t
CWL
LOW-level system clock pulse width
t
CWH
HIGH-level system clock pulse width
Serial input data timing
(see Fig.7)
T
cy(CLK)(bit)
t
CLKH(bit)
t
CLKL(bit)
t
r
t
f
t
su(i)(D)
t
h(i)(D)
t
su(WS)
t
h(WS)
Microcontroller interface timing
(see Figs 4 and 6)
bit clock period
bit clock HIGH time
bit clock LOW time
rise time
fall time
data input set-up time
data input hold time
word selection set-up time
word selection hold time
300
100
100
20
0
20
10
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
cy(CLK)(L3)
t
CLK(L3)H
t
CLK(L3)L
t
su(L3)A
t
h(L3)A
t
su(L3)D
t
h(L3)D
t
su(L3)DA
L3CLK
L3CLK HIGH period
L3CLK LOW period
L3MODE set-up time
L3MODE hold time
L3MODE set-up time
L3MODE hold time
L3DATA set-up time
500
250
250
190
190
190
190
190
ns
ns
ns
ns
ns
ns
ns
ns
addressing mode
addressing mode
data transfer mode
data transfer mode
data transfer and
addressing mode
data transfer and
addressing mode
t
h(L3)DA
L3DATA hold time
30
ns
t
stp(L3)
L3MODE halt time
190
ns
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