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參數(shù)資料
| 型號： | UDA1325PS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Universal Serial Bus USB CODEC |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 13/52頁 |
| 文件大小： | 310K |
| 代理商： | UDA1325PS |
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1999 May 10
13
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
USB ENDPOINT DESCRIPTION
The UDA1325 has following six endpoints:
USB control endpoint 0
USB control endpoint 1
USB status interrupt endpoint 1
USB status interrupt endpoint 2
Isochronous data sink endpoint
Isochronous data source endpoint.
Table 5
Endpoint description
CONTROLLING THE PLAYBACK FEATURES
Controlling the playback features of the ADAC
The exchange of control information between the microcontroller and the ADAC is accomplished through a serial
hardware interface comprising the following pins:
L3_DATA: microcontroller interface data line
L3_MODE: microcontroller interface mode line
L3_CLK: microcontroller interface clock line.
See also the description of Port 3 of the 80C51 microcontroller.
Information transfer through the microcontroller bus is organized in accordance with the so-called ‘L3’ format, in which
two different modes of operation can be distinguished; address mode and data transfer mode.
The address mode is required to select a device communicating via the L3-bus and to define the destination registers
for the data transfer mode. Data transfer for the UDA1325 can only be in one direction, from microcontroller to ADAC to
program its sound processing features and other functional features.
A
DDRESS MODE
The address mode is used to select a device (in this case the ADAC) for subsequent data transfer and to define the
destination registers. The address mode is characterized by L3_MODE being LOW and a burst of 8 pulses on L3_CLK,
accompanied by 8 data bits on L3_DATA. Data bits 0 and 1 indicate the type of the subsequent data transfer as shown
in Table 6.
ENDPOINT
NUMBER
ENDPOINT
INDEX
ENDPOINT TYPE
DIRECTION
MAX. PACKET
SIZE (BYTES)
0
0
1
2
3
4
5
6
7
control (default)
out
in
out
in
in
in
out
in
8
8
8
8
8
8
336
336
1
control
2
3
4
5
interrupt
interrupt
isochronous out
isochronous in
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