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參數資料
| 型號： | UDA1340M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Low-voltage low-power stereo audio CODEC with DSP features |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數： | 17/24頁 |
| 文件大小： | 154K |
| 代理商： | UDA1340M |
1997 Jul 09
17
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1340
AC CHARACTERISTICS (DIGITAL)
V
DDD
= V
DDA
= V
DDO
= 2.7 to 3.6 V; T
amb
=
20 to +85
°
C; R
L
= 5 k
; all voltages referenced to ground
(pins 1, 11, 22 and 27); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
T
cy
clock cycle
f
sys
= 256f
s
f
sys
= 384f
s
f
sys
= 512f
s
f
sys
< 19.2 MHz
f
sys
≥
19.2 MHz
f
sys
< 19.2 MHz
f
sys
≥
19.2 MHz
78
52
39
30
40
30
40
88
59
44
131
87
66
70
60
70
60
ns
ns
ns
%T
sys
%T
sys
%T
sys
%T
sys
t
CWL
f
sys
LOW level pulse width
t
CWH
f
sys
HIGH level pulse width
Serial input/output data timing;
see Fig.7
t
BCK
t
BCK(H)
t
BCK(L)
t
r
t
f
t
s;DATI
t
h;DATI
t
d(DATO)(BCK)
t
d(DATO)(WS)
t
h;DATO
t
s;WS
t
h;WS
bit clock period
bit clock HIGH time
bit clock LOW time
rise time
fall time
data input set-up time
data input hold time
data output delay time (from BCK falling edge)
data output delay time (from WS edge)
data output hold time
word selection set-up time
word selection hold time
1
64
f
s
100
100
20
0
0
20
10
20
20
80
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSB-justified format
Address and data transfer mode timing;
see Figs 4 and 5
T
cy
t
HC
t
LC
t
s;MA
t
h;MA
t
s;MT
t
h;MT
t
s;DAT
L3CLK cycle time
L3CLK HIGH period
L3CLK LOW period
L3MODE set-up time
L3MODE hold time
L3MODE set-up time
L3MODE hold time
L3DATA set-up time
500
250
250
190
190
190
190
190
ns
ns
ns
ns
ns
ns
ns
ns
address mode
address mode
data transfer mode
data transfer mode
data transfer mode
and address mode
data transfer mode
and address mode
t
h;DAT
L3DATA hold time
30
ns
t
halt
L3MODE halt time
190
ns
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