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參數資料
| 型號： | UDA1344 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | Low-voltage low-power stereo audio CODEC with DSP features |
| 中文描述： | 低電壓低功耗立體聲音頻編解碼器與數字信號處理功能 |
| 文件頁數： | 7/28頁 |
| 文件大小： | 126K |
| 代理商： | UDA1344 |
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2000 Feb 04
7
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output on pin DATAO is held
at LOW level until valid data is available from the
decimation filter. This time depends on whether the
DC-cancellation filter is selected:
DC cancel off:
f
s
; t = 23.2 ms at f
s
= 44.1 kHz
DC cancel on:
1f
=
; t = 279 ms at f
s
= 44.1 kHz.
Interpolation filter (DAC)
The digital filter interpolates from 1f
s
to 128f
s
by means of
a cascade of a recursive filter and an FIR filter.
Table 4
Interpolation filter characteristics
Noise shaper (DAC)
The 3rd-order noise shaper operates at 128f
s
. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSDAC).
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
ITEM
CONDITIONS
0
0.45f
s
>0.55f
s
0
0.45f
s
DC
VALUE (dB)
±
0.03
50
108
3.5
Pass-band ripple
Stop band
Dynamic range
Gain
t
1024
=
t
s
Multiple format input/output interface
The UDA1344TS supports the following data input/output
formats:
I
2
S-bus format with data word length of up to 20 bits
MSB-justifiedserial formatwith datawordlength ofupto
20 bits
LSB-justified serial format with data word lengths of
16, 18 or 20 bits (in L3 mode only)
Combined data formats:
– L3 mode: MSB-justified data output and
LSB-justified 16, 18 and 20 bits data input
– Static pin mode: MSB-justified data output and
LSB-justified 16 and 20 bits data input.
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
Control mode selection
The UDA1344TS can be used under L3 microcontroller
interface control or static pin control. The mode can be set
via the mode control pins MC1 and MC2 (see Table 5).
Table 5
Mode control pins
Important:
in the L3 mode the UDA1344TS is completely
pin and function compatible with the UDA1340M.
PIN MC2
PIN MC1
MODE
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
L3 mode
Test mode
Static pin mode
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1344TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-voltage low-power stereo audio CODEC with DSP features |
| UDA1344TS/N2 | 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO W/DSP 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, W/DSP, 28-SSOP |
| UDA1344TS/N2,512 | 功能描述:接口—CODEC AUDIO CODEC W/DSP RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1344TS/N2,518 | 功能描述:接口—CODEC AUDIO CODEC-LO VOLT RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1344TSDB | 功能描述:接口—CODEC AUDIO CODEC W/DSP RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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