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參數(shù)資料
型號: UDA1351H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: 96 kHz IEC 958 audio DAC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 15/36頁
文件大小: 157K
代理商: UDA1351H
2000 Feb 18
15
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
8.6.2
L3
CONTROL MODE
The L3 control mode allows maximum flexibility in controlling the UDA1351H.
It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and
that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface.
Also it should be noted that in using the L3 control mode, an initialization string is needed after power-up of the device
for reliable operation.
Table 4
Pin description in the L3 control mode
PIN
NAME
VALUE
FUNCTION
Mode selection pin
35
SELSTATIC
0
select L3 control mode; must be connected to V
SDD
Input pins
1
RESET
0
1
normal operation
reset
must be connected to the L3-bus
must be connected to the L3-bus
must be connected to the L3-bus
5
6
10
L3DATA
L3CLOCK
L3MODE
Status pins
21
LOCK
0
1
00
01
10
11
clock regeneration or IEC 958 decoder out-of-lock
clock regeneration and IEC 958 decoder locked
IEC 958 input: no-pre-emphasis
IEC 958 input: f
s
= 32.0 kHz with pre-emphasis
IEC 958 input: f
s
= 44.1 kHz with pre-emphasis
IEC 958 input: f
s
= 48.0 kHz with pre-emphasis
30 and 42 PREEM1 and
PREEM0
Test pins
23
34
39
44
TC
TEST1
TEST2
RTCB
0
1
0
0
must be connected to ground (V
SSD
)
must be connected to supply voltage (V
DDD
)
must be connected to ground (V
SSD
)
must be connected to ground (V
SSD
)
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