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參數資料
| 型號： | UL631H256S2K35 |
| 英文描述： | SimtekLow Voltage SoftStore 32K x 8 nvSRAM |
| 中文描述： | SimtekLow電壓SoftStore 32K的× 8非易失 |
| 文件頁數： | 5/13頁 |
| 文件大小： | 190K |
| 代理商： | UL631H256S2K35 |
UL631H256
5
March 31, 2006
STK Control #ML0057
Rev 1.0
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
No.Write Cycle
Symbol
35
45
Unit
Alt. #1
Alt. #2
IEC
Min.
Max.
Min.
Max.
12 Write Cycle Time
t
AVAV
t
AVAV
t
cW
35
45
ns
13 Write Pulse Width
t
WLWH
t
w(W)
25
30
ns
14 Write Pulse Width Setup Time
t
WLEH
t
su(W)
25
30
ns
15 Address Setup Time
t
AVWL
t
AVEL
t
su(A)
0
0
ns
16 Address Valid to End of Write
t
AVWH
t
AVEH
t
su(A-WH)
25
30
ns
17 Chip Enable Setup Time
t
ELWH
t
su(E)
25
30
ns
18 Chip Enable to End of Write
t
ELEH
t
w(E)
25
30
ns
19 Data Setup Time to End of Write
t
DVWH
t
DVEH
t
su(D)
12
15
ns
20 Data Hold Time after End of Write
t
WHDX
t
EHDX
t
h(D)
0
0
ns
21 Address Hold after End of Write
t
WHAX
t
EHAX
t
h(A)
0
0
ns
22 W LOW to Output in High-Z
h, i
t
WLQZ
t
dis(W)
13
15
ns
23 W HIGH to Output in Low-Z
t
WHQX
t
en(W)
5
5
ns
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
t
a(A)
Previous Data Valid
Output Data Valid
t
cR
Address Valid
t
v(A)
Ai
DQi
Output
(1)
(2)
(9)
Ai
E
G
DQi
Output
t
dis(E)
t
cR
t
a(E)
t
en(E)
t
en(G)
t
a(G)
t
dis(G)
Output Data Valid
High Impedance
I
CC
ACTIVE
STANDBY
t
PD
t
PU
(1)
(3)
(4)
(5)
(7)
(6)
(8)
(10)
(11)
t
a(A)
(2)
Address Valid
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UL631H256S2K35G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256S2K45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256S2K45G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256SC35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256SC35G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
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