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參數資料
| 型號： | UMA1005T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Dual low-power frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PDSO20 |
| 文件頁數： | 12/24頁 |
| 文件大小： | 88K |
| 代理商： | UMA1005T |
November 1994
12
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
S
PEED
-
UP MODE
In ‘speed-up mode’ the current in output PHP is:
I
PHP(S)
= I
PHP(N)
+ I
pump11
+ I
comp11
.
Where:
I
pump11
= I
pump10
×
2
(CL + 1)
; charge pump current.
I
comp11
= I
comp10
×
2
(CL + 1)
; fractional compensation
current.
In ‘speed-up mode’ the current in output PHI is:
I
PHI(S)
= I
pump21
+ I
comp21
.
Where:
I
pump21
= I
pump11
×
CK; charge pump current.
I
comp21
= I
comp11
×
CK; fractional compensation current.
Figure 7 shows that for a proper fractional compensation
the area of the fractional compensation current pulse must
be equal to the area of the charge pump ripple output. This
means that the current setting on the inputs RN and RF
I
I
RF
must have following ratio:
.
Where:
Q = fractional-N modulus.
f
VCO
= f
i(max)1
×
N; input frequency of the prescaler.
f
i(max)1
= maximum input frequency of the main divider
(pins INM1 and INM2).
f
i(max)2
= maximum input frequency of the reference
divider (pin INR).
Lock detect
The output LOCK is HIGH when the auxiliary phase
detector and the main phase detector indicate a lock
condition. The lock condition is defined as a phase
difference of less than
±
1 cycle on the reference input INR.
The lock condition is also fulfilled when the relative counter
is disabled (EM = 0 or EA = 0 respectively) for the main or
auxiliary counter respectively.
--------
29
Q
×
CN
VCO
f
i max
64
)
2
×
-----------------------------f
=
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| UMA1014 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-power frequency synthesizer for mobile radio communications |
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