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參數資料
| 型號： | UPA1742TP |
| 廠商： | NEC Corp. |
| 英文描述： | SWITCHING N-CHANNEL POWER MOSFET |
| 中文描述： | 開關N溝道功率MOSFET |
| 文件頁數： | 1/7頁 |
| 文件大?。?/td> | 80K |
| 代理商： | UPA1742TP |
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS FIELD EFFECT TRANSISTOR
μ
PA1742TP
SWITCHING
N-CHANNEL POWER MOS FET
DATA SHEET
Document No. G16325EJ1V0DS00 (1st edition)
Date Published April 2003 NS CP(K)
Printed in Japan
2002
DESCRIPTION
The
μ
PA1742TP is N-channel MOS FET device that
features a low on-state resistance and excellent switching
characteristics, and designed for high voltage applications
such as DC/DC converter.
FEATURES
High voltage: V
DSS
= 250 V
Gate voltage rating: ±30 V
Low on-state resistance
R
DS(on)
= 0.55
MAX. (V
GS
= 10 V, I
D
= 3.5 A)
Low input capacitance
C
iss
= 460 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
Built-in gate protection diode
Small and surface mount package (Power HSOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
μ
PA1742TP
Power HSOP8
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, unless otherwise noted. All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
V
DSS
Gate to Source Voltage (V
DS
= 0 V)
V
GSS
Drain Current (DC) (T
C
= 25°C)
I
D(DC)
Drain Current (pulse)
Note1
I
D(pulse)
Total Power Dissipation (T
C
= 25°C)
P
T1
Total Power Dissipation (T
A
= 25°C)
Note2
P
T2
Channel Temperature
T
ch
Storage Temperature
T
stg
55 to +150
Single Avalanche Current
Note3
I
AS
Single Avalanche Energy
Note3
E
AS
Repetitive Avalanche Current
Note4
I
AR
Repetitive Pulse Avalanche Energy
Note4
E
AR
Notes 1.
PW
≤
10
μ
s, Duty Cycle
≤
1%
2.
Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm
3.
Starting T
ch
= 25°C, V
DD
= 125 V, R
G
= 25
, L = 100
μ
H, V
GS
= 20
→
0 V
4.
T
ch(peak)
≤
150°C, L = 100
μ
H
250
±30
±7.0
±21
24
1.0
150
V
V
A
A
W
W
°C
°C
A
mJ
A
mJ
7.0
4.9
7.0
4.9
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
PACKAGE DRAWING (Unit: mm)
1.27 TYP.
0.12 M
6.0 ±0.3
4.4 ±0.15
1
2.0 ±0.2
0.8 ±0.2
0.40
+0.10
5.2
+0.17
–0.2
0
1
1
0
+
–
1
4
8
5
1, 2, 3
4
5, 6, 7, 8, 9 ; Drain
; Source
; Gate
1
4
8
5
4.1 MAX.
9
2
S
0.10
S
EQUIVALENT CIRCUIT
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
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