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參數資料
| 型號： | UPC4092 |
| 廠商： | NEC Corp. |
| 英文描述： | J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER |
| 中文描述： | J - FET輸入低偏移雙路運算放大器 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 87K |
| 代理商： | UPC4092 |
The information in this document is subject to change without notice.
BIPOLAR ANALOG INTEGRATED CIRCUIT
μ
PC4092
J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER
Document No. G13905EJ1V0DS00 (1st edition)
Date Published December 1998 N CP(K)
Printed in Japan
DATA SHEET
1998
The
μ
PC4092 dual operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable
AC operating characteristics. NEC's unique high-speed PNP transistor (f
T
= 300 MHz) in the output stage solves the
oscillation problem of current sinking with a large capacitive load. Zener-zap resistor trimming in the input stage
produces excellent offset voltage and temperature drift characteristics.
FEATURES
Stable operation with 10000 pF capacitive load
Low input offset voltage
±
3 mV (MAX.)
±
7
μ
V/°C (TYP.) temperature drift
Very low input bias and offset currents
Low noise : e
n
= 19 nV/
√
Hz (TYP.)
Output short circuit protection
High input impedance ... J-FET Input Stage
Internal frequency compensation
High slew rate: 15 V/
μ
s (TYP.)
ORDERING INFORMATION
Part Number
Package
μ
PC4092C
8-pin plastic DIP (300 mil)
μ
PC4092G2
8-pin plastic SOP (225 mil)
EQUIVALENT CIRCUIT (1/2 Circuit)
PIN CONFIGURATION
(Top View)
I
I
I
N
Q
1
Q
2
Q
4
Q
5
Q
8
D
1
C
1
Q
10
V
+
V
OUT
Q
9
Q
7
Q
6
Q
3
TRIMMED
HIGH SPEED
PNP
PC4092C, 4092G2
μ
1
1
2
3
4
8
7
6
5
V
+
OUT
2
I
I2
I
N2
+
I
I1
I
N1
OUT
1
V
2
+
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UPC4092C | 制造商:NEC 制造商全稱:NEC 功能描述:J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER |
| UPC4092G2 | 制造商:NEC 制造商全稱:NEC 功能描述:J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER |
| UPC4092G2-A | 制造商:Renesas Electronics Corporation 功能描述:SEMICONDUCTOR, IC, OP AMP, VOLTAGE, FEED |
| UPC4093 | 制造商:NEC 制造商全稱:NEC 功能描述:Bipolar Analog Integrated Circuits |
| UPC4093C | 制造商:NEC 制造商全稱:NEC 功能描述:J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER |
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