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參數資料
| 型號： | UPC8126K-E1 |
| 廠商： | NEC Corp. |
| 英文描述： | RELAY OPTOMOS SOP 4-PIN 150MA |
| 中文描述： | 900兆赫頻帶直接正交調制器集成電路的數字移動通信系統 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 67K |
| 代理商： | UPC8126K-E1 |
UPC8125GR
SILICON MMIC UPCONVERTER
WITH AGC + IQ MODULATOR
FEATURES
WIDE SUPPLY VOLTAGE RANGE:
2.7 to 5.5 V
OUTPUT FREQUENCY RANGE:
1.8 to 2.0 GHz
INTERNAL LPF TO REJECT LO & SPURIOUS
LEAKAGE
PORTS FOR EXTERNAL IF FILTER
AGC FUNCTION: 40 dB RANGE
POWER SAVE FUNCTION
SMALL 20 PIN SSOP PACKAGE
TAPE AND REEL PACKAGING AVAILABLE
INTERNAL BLOCK DIAGRAM
(Top View)
Notes:
1. P
IFIN
= -20 dBm
2. V
I/Q
= 1.5 V (DC) +0.5 Vp-p (AC)
ELECTRICAL CHARACTERISTICS
(T
A
= 25
°
C, V
CC
= 3.0 V, unless otherwise specified)
DESCRIPTION
The UPC8125GR is a Silicon MMIC manufactured with the
NESAT III
TM
silicon bipolar process. The IC consists of a 1.8 -
2.0 GHz upconverter with AGC function and a 220 - 270 MHz IQ
modulator. The device operates over a wide 2.7 - 5.5 V supply
voltage range and features a power save function. The device
was specifically designed for digital mobile communication
applications such as 1900 MHz PCS and PHS handsets.
NEC's stringent quality assurance and test procedures ensure
the highest reliability and performance.
California Eastern Laboratories
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
x 2
90 deg. Phase
Shifter (
÷
2)
LPF
LPF
Reg.
Reg.
Vcc (MOD)
Vcc (Up-con)
RFout
GND
GND
Vps
VAGC
GND
Lo2 in
Lo2 inb
GND
Filter 1
Filter 2
I
Ib
Q
Qb
Lo1 in
Lo1 inb
GND
PART NUMBER
PACKAGE OUTLINE
PARAMETERS AND CONDITIONS
Total Circuit Current (no input signal)
UPC8125GR
S20 (SSOP 20)
TYP
36
SYMBOLS
I
CC
UNITS
mA
MIN
MAX
I
CC(PS)
Total Circuit Current at Sleep Mode
V
PS
≤
0.5 V (Low)
μ
A
0.3
10
P
RFout 1
Total Output Power 1
V
AGC
= 3.0 V
dBm
-10
P
RFout 2
Total Output Power 2
V
AGC
= 0.5 V
dBm
-50
LOL
Lo Carrier Leak
f
LO
1 + f
LO
2
dBc
-37
-30
ImR
Image Rejection (Side Band leak)
dBc
-35
-30
IM
3 I/Q
I/Q 3rd Order Intermodulation Distortion
2
dBc
-50
-30
GCR
AGC Amp. Gain control range
V
AGC
= 3 V to 0.5 V
dB
25
40
T
PS(RISE)
Power Save Rise Time
V
PS
(OFF)
→
V
PS
(ON)
μ
S
2
5
T
PS
(FALL)
Power Save Fall Time
V
PS
(ON)
→
V
PS
(OFF)
μ
S
2
5
Z
I/Q
Input Impedance I and Q Ports
2
f
I/Q
= 24 KH
Z
,I
→
Ib,Q
→
Qb
k
200
I
I/Q
I/Q Bias Current
I
→
Ib,Q
→
Qb
μ
A
5
Z
LO
1
Lo1 Input VSWR
f
LO
1= 220 MHz
to 270 MHz
1.2:1
EVM
Error Vector Magnitude
MOD Pattern : PN9
%rms
2.5
Padj
Adjacent Channel Power
f = 600 KH
Z
MOD Pattern : PN9
dBc
-68
U
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