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參數資料
| 型號： | UPD44324092F5-E37-EQ2-A |
| 廠商： | NEC Corp. |
| 元件分類： | DRAM |
| 英文描述： | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 36M條位SRAM的2條DDRII字爆發運作 |
| 文件頁數： | 1/40頁 |
| 文件大小： | 361K |
| 代理商： | UPD44324092F5-E37-EQ2-A |
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MOS INTEGRATED CIRCUIT
μ
PD
44324082, 44324092, 44324182, 44324362
36M-BIT DDRII SRAM
2-WORD BURST OPERATION
Document No. M16780EJ3V0DS00 (3rd edition)
Date Published March 2006 NS CP(K)
Printed in Japan
DATA SHEET
2003
Description
The
μ
PD44324082 is a 4,194,304-word by 8-bit, the
μ
PD44324092 is a 4,194,304-word by 9-bit, the
μ
PD44324182 is a
2,097,152-word by 18-bit and the
μ
PD44324362 is a 1,048,576-word by 36-bit synchronous double data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44324082,
μ
PD44324092,
μ
PD44324182 and
μ
PD44324362 integrate unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K
and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA package (13 x 15)
HSTL Interface
DLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
User programmable impedance output
Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
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相關PDF資料 |
PDF描述 |
|---|---|
| UPD44324092F5-E40-EQ2-A | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324092F5-E50-EQ2-A | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324182F5-E37-EQ2 | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324182F5-E37-EQ2-A | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324182F5-E40-EQ2-A | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
相關代理商/技術參數 |
參數描述 |
|---|---|
| UPD44324182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W |
| UPD44324185BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324365BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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