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參數(shù)資料
| 型號(hào)： | UPD44325184F5-E50-EQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| 中文描述： | 36M條位推出QDRII SRAM的4個(gè)字爆發(fā)運(yùn)作 |
| 文件頁(yè)數(shù)： | 1/36頁(yè) |
| 文件大小： | 377K |
| 代理商： | UPD44325184F5-E50-EQ2 |
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MOS INTEGRATED CIRCUIT
μ
PD
44325084, 44325094, 44325184, 44325364
36M-BIT QDR
TM
II SRAM
4-WORD BURST OPERATION
Document No. M16784EJ1V0DS00 (1st edition)
Date Published October 2004 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
2003
Description
The
μ
PD44325084 is a 4,194,304-word by 8-bit, the
μ
PD44325094 is a 4,194,304-word by 9-bit, the
μ
PD44325184 is a
2,097,152-word by 18-bit and the
μ
PD44325364 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44325084,
μ
PD44325094,
μ
PD44325184 and
μ
PD44325364 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive
edge of K and /K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with
μ
s restart
User programmable impedance output
Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44325094F5-E40-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325094F5-E50-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325084 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325364F5-E50-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325084F5-E33-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44325362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325362F5-E40-EQ2 | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44325364BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325364BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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