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參數資料
型號: UPD45128163G5-A10T-9JF
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁數: 1/86頁
文件大小: 774K
代理商: UPD45128163G5-A10T-9JF
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD45128163-T
128M-bit Synchronous DRAM
4-bank, LVTTL
WTR (Wide Temperature Range)
DATA SHEET
Document No. E0348N10 (Ver.1.0)
Date Published February 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Elpida Memory, Inc. 2003
Description
The
μ
PD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as
2,097,152
×
16
×
4 (word
×
bit
×
bank).
The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).
This product is packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0(A13) and BA1(A12)
Byte control by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Ambient temperature (T
A
):
20 to + 85
°
C
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
×
16 organization
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
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相關代理商/技術參數
參數描述
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