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參數資料
| 型號： | UPD72107 |
| 廠商： | NEC Corp. |
| 英文描述： | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| 中文描述： | 鱲- B控制器（鏈路訪問過程平衡模式） |
| 文件頁數： | 1/32頁 |
| 文件大小： | 182K |
| 代理商： | UPD72107 |
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LAP-B CONTROLLER
Link Access Procedure Balanced mode
The
μ
PD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single
chip.
MOS INTEGRATED CIRCUIT
μ
PD72107
Document No. S12962EJ5V0DS00 (5th edition)
Date Published October 1998 N CP(K)
Printed in Japan
The information in this document is subject to change without notice.
1998
DATA SHEET
FEATURES
Complied with ITU-T recommended X.25 (LAP-B84
edition)
HDLC frame control
Sequence control
Flow control
ITU-T recommended X.75 supported
TTC standard JT-T90 supported
Optional functions
Option frame
Global address frame
Error check deletion frame
Powerful test functions
Data loopback function
Loopback test link function
Frame trace function
Abundant statistical information
Detailed mode setting function
Modem control function
On-chip DMAC (Direct Memory Access Controller)
24-bit address
Byte/word transfer enabled (switch with external pin)
Memory-based interface
Memory-based command
Memory-based status
Memory-based transmit/receive data
MAX.4 Mbps serial transfer rate
NRZ, NRZI coding
ORDERING INFORMATION
Part Number
μ
PD72107CW
μ
PD72107GC-3B9
μ
PD72107L
Package
64-pin plastic shrink DIP (750 mils)
80-pin plastic QFP (14 x 14 mm)
68-pin plastic QFJ (950 x 950 mils)
相關PDF資料 |
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|---|---|
| uPD72107CW | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
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