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參數(shù)資料
型號: UT54ACTS279-PCCH
元件分類: 鎖存器
英文描述: ACT SERIES, QUAD LOW LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16
封裝: DIP-16
文件頁數(shù): 1/4頁
文件大小: 37K
代理商: UT54ACTS279-PCCH
195
RadHard MSI Logic
UT54ACS279/UT54ACTS279
Radiation-Hardened
Quadruple S-R Latches
FEATURES
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS279 and the UT54ACTS279 contain four basic
S-R flip-flop latches. Under conventional operation, the S-R
inputs are normally held high. When the S input is pulsed low,
the Q output will be set high. When R is pulsed low, the Q
output will be reset low. If the S-R inputs are taken low simul-
taneously, the Q output is unpredictable.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
Note:
1. This configuration is nonstable. It may not persist when the S and R inputs
return to their inactive (high) level.
LOGIC DIAGRAM
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpack
Top View
LOGIC SYMBOL
INPUTS
OUTPUT
S
R
Q
H
H
Q
0
L
H
H
H
L
L
L
L
H
1
R
S1
S2
Q
(LATCHES 1 & 3)
R
S
Q
(LATCHES 2 & 4)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
1R
1S1
1S2
1Q
2R
2S
2Q
V
SS
V
DD
4S
4R
4Q
3S2
3S1
3R
3Q
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
4S
4R
4Q
3S2
3S1
3R
3Q
1R
1S1
1S2
1Q
2R
2S
2Q
V
SS
1Q
(4)
(7)
2Q
3Q
(9)
(13)
4Q
(1)
(2)
(3)
1R
1S1
1S2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
R
S1
S1
(5)
(6)
(10)
(11)
(12)
2R
2S
3R
3S1
3S2
R
S2
R
S3
S3
(14)
(15)
4R
4S
R
S4
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