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參數(shù)資料
| 型號(hào)： | UT54LVDS032-UPA |
| 廠商： | Aeroflex Inc. |
| 英文描述： | Quad Receiver |
| 中文描述： | 四接收機(jī) |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 78K |
| 代理商： | UT54LVDS032-UPA |
FEATURES
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>155.5 Mbps (77.7 MHz) switching rates
+340mV differential signaling
5 V power supply
TTL compatible outputs
Ultra low power CMOS technology
8.0ns maximum propagation delay
3.0ns maximum differential skew
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 111 MeV-cm
2
/mg)
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-95834
- QML Q and V compliant part
Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
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INTRODUCTION
The UT54LVDS032 Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device
is designed to support data rates in excess of 155.5 Mbps
(77.7 MHz) utilizing Low Voltage Differential Signaling
(LVDS) technology.
The UT54LVDS032 accepts low voltage (340mV)
differential input signals and translates them to 5V TTL
output levels. The receiver supports a three-state function
that may be used to multiplex outputs. The receiver also
supports OPEN, shorted and terminated (100
) input fail-
safe. Receiver output will be HIGH for all fail-safe
conditions.
The UT54LVDS032 and companion quad line driver
UT54LVDS031 provides new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
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R1
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IN1+
R
IN1-
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IN2+
R
IN2-
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IN3+
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IN3-
R
IN4+
R
IN4-
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OUT1
R
OUT2
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OUT4
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OUT3
EN
EN
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R2
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R3
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Standard Products
UT54LVDS032 Quad Receiver
Data Sheet
May 22, 2003
Figure 1. UT54LVDS032 Quad Receiver Block Diagram
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