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參數資料
| 型號： | UT7C138C45GCC |
| 英文描述： | SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC |
| 中文描述： | 靜態存儲器| 4KX8 |的CMOS | RAD數據通信硬|美巡賽| 68PIN |陶瓷 |
| 文件頁數： | 11/21頁 |
| 文件大小： | 272K |
| 代理商： | UT7C138C45GCC |
11
Address
CE
R/W
Data in
t
WC
t
SCE
t
AW
t
PWE
t
SA
t
SD
DATA
VALID
t
HA
t
LZWE
t
HD
t
HZWE
HIGH
IMPEDANCE
Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)
Assumptions:
1.
The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initialize a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the sig-
nal that terminates the write.
2. R/W must be HIGH during all address transactions.
3. Data I/O pins enter high impedance even if OE is held LOW during
write.
Data out
t
WHWL
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| UT7C138C45GCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC |
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| UT7C138C45GPX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| UT7C138C45WCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
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