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參數(shù)資料
| 型號(hào)： | UT7C138C45GPX |
| 英文描述： | x8 Dual-Port SRAM |
| 中文描述： | x8雙端口SRAM |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 272K |
| 代理商： | UT7C138C45GPX |
11
Address
CE
R/W
Data in
t
WC
t
SCE
t
AW
t
PWE
t
SA
t
SD
DATA
VALID
t
HA
t
LZWE
t
HD
t
HZWE
HIGH
IMPEDANCE
Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)
Assumptions:
1.
The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initialize a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the sig-
nal that terminates the write.
2. R/W must be HIGH during all address transactions.
3. Data I/O pins enter high impedance even if OE is held LOW during
write.
Data out
t
WHWL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UT7C138C45WCA | SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCC | SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCX | SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WPA | x8 Dual-Port SRAM |
| UT7C138C45WPC | x8 Dual-Port SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UT7C138C45WCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| UT7C138C45WPC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
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