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參數資料
| 型號： | UT7C139C55WPA |
| 英文描述： | x9 Dual-Port SRAM |
| 中文描述： | X9熱賣雙端口SRAM |
| 文件頁數： | 1/21頁 |
| 文件大?。?/td> | 272K |
| 代理商： | UT7C139C55WPA |
FEATURES
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45ns and 55ns maximum address access time
Asynchronous operation for compatibility with industry-
standard 4K x 8/9 dual-port static RAM
CMOS compatible inputs, TTL/CMOS compatible output
levels
Three-state bidirectional data bus
Low operating and standby current
Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Memory Cell LET threshold: 85 MeV-cm
2
/mg
- Latchup immune (LET >100 MeV-cm
2
/mg)
QML Q and QML V compliant part
Packaging options:
- 68-lead Flatpack
- 68-pin PGA
5-volt operation
Standard Microcircuit Drawing 5962-96845
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INTRODUCTION
The UT7C138 and UT7C139 are high-speed radiation-
hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.
Arbitration schemes are included on the UT7C138/139 to
handle situations when multiple processors access the same
memory location. Two ports provide independent,
asynchronous access for reads and writes to any location in
memory. The UT7C138/139 can be utilized as a stand-alone
32/36-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16/18-bit or wider master/
slave dual-port static RAM. For applications that require
depth expansion, the BUSY pin is open-collector allowing
for wired OR circuit configuration. An M/S pin is provided
for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications,
and status buffering.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port.
Standard Products
UT7C138/139 4Kx8/9 Radiation-Hardened
Dual-Port Static RAM with Busy Flag
Data Sheet
January 2002
Figure 1. Logic Block Diagram
MEMORY
ARRAY
ROW
SELECT
ROW
SELECT
COL
SEL
COL
SEL
COLUMN
I/O
COLUMN
I/O
R/W
L
CE
L
OE
L
A
11L
A
10L
A
9L
A
0L
R/W
R
CE
R
OE
R
A
11R
A
10R
A
9R
A
0R
I/O
7L
I/O
8L
(7C139)
I/O
7R
I/O
8R
(7C139)
I/O
0L
I/O
0R
ARBITRATION
BUSY
L
BUSY
R
M/S
相關PDF資料 |
PDF描述 |
|---|---|
| UT7C139C55WPC | x9 Dual-Port SRAM |
| UT7C139C55WPX | x9 Dual-Port SRAM |
| UT7M628-70PBH | x16 ROM (Mask Programmable) |
| UT7M628-70PBR | AMD TURION 64 |
| UT7M628-70PCH | x16 ROM (Mask Programmable) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| UT7C139C55WPC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| UT7C139C55WPX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| UT7Q512 | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:512K x 8 SRAM |
| UT7Q512-100UCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| UT7Q512-100UCC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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