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參數資料
| 型號： | V350EPC-40 |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數： | 1/18頁 |
| 文件大小： | 154K |
| 代理商： | V350EPC-40 |
Copyright 1998, V3 Semiconductor Corp.
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V350EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
V350EPC Data Sheet Rev 1.1
1
V350EPC
Rev. A0
LOCAL BUS TO PCI BRIDGE
FOR MULTIPLEXED A/D PROCESSORS
Glueless interface to Intel’s i960Jx and IBM’s
PowerPC
TM
401Gx processors
Configurable for primary master, bus master or
target operation.
Type 0 and type 1 configuration cycles.
Up to 1Kbyte burst access on PCI or local.
Large, 640-byte FIFOs using V3’s unique
D
YNAMIC
B
ANDWIDTH
A
LLOCATION
architecture
64-byte read FIFO per aperture.
Enhanced support for 8/16-bit local bus devices
with programmable region sizes.
3.3 volt support
Dual bi-directional address space remapping
Fully compliant with PCI 2.1 specification
On-the-fly byte order (endian) conversion
I
2
O ATU and messaging unit including
hardware controlled circular queues
2 channel DMA controller plus multiprocessor
DMA chaining and demand mode DMA
Hot swapping capability
16 8-bit bi-directional mailbox registers with
doorbell interrupts
Flexible PCI and local interrupt management
Optional power-on serial EEPROM initialization
33MHz and 40MHz local bus versions
Industrials temperature grade -40 to +85’C
Low cost 160-pin EIAJ PQFP package
V350EPC is a high-performance and low-cost
generic solution for interfacing both 32-bit and
16-bit multiplexed local bus applications to the
PCI bus. V350EPC directly connects to i960Jx or
i960Sx processors without any glue logic.
Minimal glue logic is required for high-
performance interfacing to other multiplexed
processors like Motorola ColdFire
.
V350EPC is the second generation of V3’s I
2
O
ready PCI bridges - fully backward compatible
with both V961PBC and V960PBC Rev B2
devices - and is supporting powerful features like
Hot Swap and DMA chaining. The PCI bus can
be run at the full 33MHz frequency, independent
of local bus clock rate. The overall throughput of
the system is dramatically improved by
increasing the FIFO depths and utilizing the
unique
D
YNAMIC
B
ANDWIDTH
A
LLOCATION
architecture.
Access to the PCI bus can be performed through
two programmable address apertures. Two more
apertures are provided for PCI-to-local bus
accesses. There are 64-bytes of read FIFOs in
each direction, 32-byte dedicated for each
aperture .
Two high-performance DMA channels with
chaining and demand mode capabilities provide
a powerful data transfer engine for bulk data
transfers. Mailbox registers and flexible PCI
interrupt controllers are also included to provide
a simple mechanism to emulate PCI device
control ports. The part is available in 160-pin low
cost PQFP packages in 33MHz and 40MHz
versions.
i960Jx
CPU
V96BMC
MEMORY
CONTROL
D
R
A
M
ROM
V350EPC
LOCAL TO
PCI BRIDGE
TYPICAL APPLICATION
PERIPHERAL
PCI
PCI SLOT or EDGE CONNECTOR
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