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參數資料
| 型號： | V62/08627-01XE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 1/25頁 |
| 文件大小： | 675K |
| 代理商： | V62/08627-01XE |
1
FEATURES
APPLICATIONS
DESCRIPTION/ORDER INFORMATION
www.ti.com....................................................................................................................................................................................................... SLLS882 – JUNE 2008
3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS
Signaling Rate 0 Mbps to 150 Mbps
23
Controlled Baseline
–
Low Propagation Delay
–
One Assembly Site
–
Low Pulse Skew (Pulse-Width Distortion)
–
One Test Site
Low-Power Sleep Mode
–
One Fabrication Site
High Electromagnetic Immunity
Extended Temperature Performance of
Low Input Current Requirement
–55°C to 125°C
Failsafe Output
Enhanced Diminishing Manufacturing Sources
Drop-In Replacement for Most Opto and
(DMS) Support
Magnetic Isolators
Enhanced Product-Change Notification
Industrial Fieldbus
Qualification Pedigree (1)
–
Modbus
4000-V
(peak) Isolation
–
Profibus
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
–
DeviceNet Data Buses
IEC 61010-1
–
Smart Distributed Systems (SDS)
–
50-kV/
s Transient Immunity Typical
Computer Peripheral Interface
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
Servo Control Interface
extended temperature range. This includes, but is not limited
Data Acquisition
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated
by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits
from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received for more than 4
s, the input is assumed
to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SDS is a trademark of Honeywell.
3
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
UNLESS
OTHERWISE
NOTED
this
document
contains
Copyright 2008, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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