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參數資料
| 型號： | VG4632321A |
| 廠商： | Vanguard International Semiconductor Corporation |
| 英文描述： | CHASSIS PLATE; IP rating:IP67; Temp, op. max:100(degree C); Temp, op. min:-40(degree C) RoHS Compliant: Yes |
| 中文描述： | 524,288 x32x2位CMOS同步圖形內存 |
| 文件頁數： | 1/81頁 |
| 文件大小： | 1965K |
| 代理商： | VG4632321A |
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Document:
Rev.1
Page 1
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Overview
The VG4632321A SGRAM is a high-speed CMOS synchronous graphic RAM containing 32M bits. It is
internally configured as a dual 512K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 512K x 32 bit bank is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4632321A provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with
burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy
to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
Fast access time from clock: 4.5/5/5.5/6/7ns
Fast clock rate: 222/200/183/166/143MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks(512K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single + 3.3V
power supply
Interface: LVTTL
JEDEC 100-pin Plastic QFP package
0.3V
±
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
DQ16
DQ17
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ18
V
DDQ
V
DD
V
SS
DQ20
V
SSQ
DQ22
V
DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BS
A9
DQ28
V
DDQ
DQ27
DQ26
V
DQ25
DQ24
V
DQ15
DQ14
V
DQ13
DQ12
V
DDQ
V
SS
V
DQ11
DQ10
V
DQ9
DQ8
V
DDQ
NC
DQM3
DQM1
CLK
CKE
DSF
NC
A8/AP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
D
V
S
D
D
V
S
N
N
N
N
N
N
N
N
N
D
D
D
N
V
D
V
S
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
1
8
A
A
A
A
V
S
A
N
N
N
N
N
N
N
N
A
A
A
N
V
D
A
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
5
Pin Assignment (Top View)
Key Specifications
VG4632321A
-4.5/-5/-5.5/-6/-7
t
CK
Clock Cycle time(min.)
4.5/5/5.5/6/7 ns
t
RAS
Row Active time(min.)
40/40/40/42/42 ns
t
AC
Access time from CLK(max.)
4/4.5/5/5.5/6 ns
t
RC
Row Cycle time(min.)
55/55/56.5/60/62 ns
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