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參數(shù)資料
| 型號： | VP520S |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | PAL/NTSC to CIF/QCIF Converter(PAL/NTSC和CIF/QCIF轉換器) |
| 中文描述： | PAL / NTSC制式的到岸價格/ QCIF的轉換器（PAL / NTSC制式和到岸價格/ QCIF的轉換器） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 162K |
| 代理商： | VP520S |
1
VP520S
PAL/NTSC to CIF/QCIF Converter
Advance Information
Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2
DS3504 - 3.2 October 1996
FEATURES
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Lower Power, pin compatible replacement for VP520
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Converts CCIR601 luminance and chrominance to CIF
or QCIF resolution, and vice versa, using a 27MHz
system clock.
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Luminance and chrominance channels have their own
sets of horizontal and vertical filters with on chip line
stores
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Each filter set may be configured to either decimate or
interpolate.
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NTSC line insertion or removal mode
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Produces / expects CIF/QCIF data in macroblock for-
mat.
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120 Pin QFP Package
Fig 1 : Simplified Block Diagram
DESCRIPTION
The VP520S is designed to convert 16 bit multiplexed
luminance and chrominance data between CCIR601 and CIF/
QCIF resolutions. Vertical and horizontal FIR filters are pro-
vided, with the vertical filters supported by on chip line stores.
The coefficients used by the filters are user definable, and are
down loaded from an independent host data bus. An internal
address generator supports an external DRAM frame store,
and also provides line to macroblock conversion.
When producing CIF or QCIF video the horizontal filters
precede the vertical filters, and are provided with between 8
and 16 taps. The vertical filters are provided with four CIF line
delays which allow a 5 tap filter to be implemented. When
producing QCIF the available RAM is used to provide six line
delays, which thus allows 7 tap filters to be used.
When the device is producing CCIR601 video, the incom-
ing data must be in macroblock format, and the vertical filters
precede the horizontal filters The inputs are firstly written to a
external CIF sized frame store, and are read out in line format.
The VP520S will support two complete frame stores, and
allows the CIF/QCIF data to be read out twice in order to
produce two interlaced fields of video.
The VP520S supports the conversion between CIF/QCIF
and NTSC video. An extra line is produced for every five lines
when producing CIF data, and one line in six is removed when
producing NTSC video. Poly phase filters are used to provide
the correct decimation and interpolation ratios.
ASSOCIATED PRODUCTS
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VP510 Colour Space Converter
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VP2611 H261 Encoder
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VP2615 H261 Decoder
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VP2612 Video Multiplexer
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VP2614 Video Demultiplexer
FRAME START
/ READY
16 BIT
FRAME STORE
BUS
RAM ADDRESS
GENERATOR
SUPPORTING
LINE TO BLOCK
CONVERSION
Horizontal
Filters
Vertical
Filters
FOUR
LINE
DELAYS
FILTER BLOCK
INPUT/
OUTPUT
FIFO
MUXING
FILTER BLOCK
FILTER BLOCK
VP520S
8 BIT
LUMINANCE
CREF
8 BIT
MACROBLOCK
BUS
COEFF
STORE
HOST
BUS
ADDRESS
CONTROL
SYNC
GENERATOR
HREF
VREF
MUX
8 BIT
CHROMINANCE
MACROBLOCK
STROBE
REQ BLKS
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| VP520SCG | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:PAL/NTSC to CIF/QCIF Converter |
| VP520SCGGH1R | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:PAL/NTSC to CIF/QCIF Converter |
| VP5225 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:P-Channel Enhancement-Mode Vertical DMOS FET |
| VP5225K4 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:P-Channel Enhancement-Mode Vertical DMOS FET |
| VP5225K4-G | 功能描述:MOSFET P-CH -250V 3.0 MOSFET RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
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