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參數資料
| 型號： | W162-19G |
| 英文描述： | NINE DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SOP|16PIN|PLASTIC |
| 中文描述： | 第九分布式輸出時鐘驅動器|的CMOS |?？苵 16PIN |塑料 |
| 文件頁數： | 1/7頁 |
| 文件大?。?/td> | 131K |
| 代理商： | W162-19G |
Spread Aware, Zero Delay Buffer
W162
Cypress Semiconductor Corporation
Document #: 38-07150 Rev. **
3901 North First Street
San Jose
CA 95134
Revised November 14, 2001
408-943-2600
Features
Spread Aware—designed to work with SSFTG
reference signals
Two banks of four outputs, plus the fed back output
Outputs may be three-stated
Available in 16-pin SOIC or SSOP package
Extra strength output drive available (-19 version)
Internal feedback
Key Specifications
Operating Voltage: ............................................... 3.3V±10%
Operating Range: ................................15 < f
OUT
< 133 MHz
Cycle-to-Cycle Jitter: .................................................. 250 ps
Output to Output Skew: ............................................. 150 ps
Propagation Delay: ..................................................... 150 ps
Table 1. Input Logic
SEL1
0
SEL0
0
QA0:3
Three-
State
Active
QB0:3
Three-
State
Three-
State
Active
PLL
QFB
Active
Shutdown
0
1
Active,
Utilized
Shutdown,
Bypassed
Active,
Utilized
Active
1
0
Active
Active
1
1
Active
Active
Active
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Block Diagram
Pin Configuration
PLL
REF
MUX
QA1
QA2
QA3
QB0
QB1
SEL0
QB2
QB3
SEL1
QFB
QA3
QA2
VDD
GND
QB3
QB2
SEL0
16
15
14
13
12
11
10
9
REF
QA0
QA1
VDD
GND
QB0
QB1
SEL1
1
2
3
4
5
6
7
8
QFB
QA0
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