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參數資料
| 型號： | W191 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 126K |
| 代理商： | W191 |
Skew Controlled SDRAM Buffer
W191
Cypress Semiconductor Corporation
Document #: 38-07008 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 17, 2002
408-943-2600
Features
Six skew controlled CMOS outputs
Output skew between any two outputs is less than
150 ps
SMBus Serial configuration interface
2.5 ns to 5 ns propagation delay
DC to 133 MHz operation (Commercial)
DC to 100 MHz operation (Industrial)
Single 3.3V supply voltage
Low power CMOS design packaged in a 16-pin SSOP
(Small Shrink Outline Package)
Key Specifications
Supply Voltages:...................................... V
DDQ3
= 3.3V ±5%
Operating Temperature: (Commercial)............. 0
°
C to +70
°
C
Operating Temperature:
(Industrial) .............
–
40
°
C to +85
°
C
Input Threshold: ..................................................1.5V typical
Maximum Input Voltage:...................................V
DDQ3
+ 0.5V
Input Frequency: (Commercial)........................ 0 to 133 MHz
Input Frequency: (Industrial) ............................ 0 to 100 MHz
BUF_IN to SDRAM0:5 Propagation Delay:......2.5 ns to 5 ns
Min. Output Edge Rate:............................................. 1.0V/ns
Max. Output Skew:......................................................150 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance:...................................................15
typ.
Block Diagram
Pin Configuration
[1]
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SMBus
SCLOCK
SDATA
Device Control
BUF_IN
VDDQ3
SDRAM5
GND
SDRAM4
VDDQ3
SDRAM3
GND
SCLK
16
15
14
13
12
11
10
9
SDRAM0
GND
SDRAM1
BUF_IN
GND
SDRAM2
VDDQ3
SDATA
1
2
3
4
5
6
7
8
Note:
1.
Internal pull-up resistor of 250K on SDATA and SCLK.
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