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參數資料
| 型號： | W208D |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 169K |
| 代理商： | W208D |
PRELIMINARY
FTG for Integrated Core Logic with 133-MHz FSB
W208D
Cypress Semiconductor Corporation
Document #: 38-07228 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Low jitter and tightly controlled clock skew
Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
Three copies of CPU clock at 66/100 MHz
Nine copies of 100-MHz SDRAM clocks
Eight copies of PCI clock
Two copies of synchronous APIC clock
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
Two copies of 66-MHz fixed clock
One copy of 14.31818-MHz reference clock
Power down control
I
2
C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, 48-MHz, SDRAM Output Skew:........................250 ps
CPU, 3V66 Output Skew:............................................175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................
±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
I
2
C is a trademark of Phillips Corporation. Intel is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Functions
SEL133
SEL1
X
0
X
0
0
1
0
1
1
1
1
1
SEL0
0
1
0
1
0
1
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Reserved
133-MHz CPU
Block Diagram
Pin Configuration
VDDQ3
VDDQ2
CPU2_ITP
PCI0_ICH
XTAL
OSC
PLL REF FREQ
PLL 1
X2
X1
REF/SEL133
PCI1:7
USB
DOT
PLL2
VDDQ3
I
2
C
Logic
SDATA
SCLK
3V66_0:1
CPU0:1
SEL0:1
APIC0:1
Divider,
Delay,
and
Phase
Control
Logic
7
2
VDDQ3
2
2
DCLK
SDRAM0:7
8
PWRDWN#
REF/SEL133*
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDDQ3
GND
GND
USB
DOT
VDDQ3
SEL0
W
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
PWRDWN#
SCLK
SDATA
SEL1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Note:
1.
Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
[1]
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