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參數(shù)資料
| 型號： | W218 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 175K |
| 代理商： | W218 |
FTG for Integrated Core Logic with 133-MHz FSB
W218
Cypress Semiconductor Corporation
Document #: 38-07221 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Three copies of CPU clock at 66/100/133 MHz
Nine copies of 100-MHz SDRAM clocks
Seven copies of PCI clock
Two copies of APIC clock at 33 MHz, synchronous to
CPU clock
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
Three copies of 3V 66-MHz fixed clock
One copy of 14.31818-MHz reference clock
Power down control
SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, SDRAM Output Skew:...................................... 250 ps
CPU, 3V66 Output Skew:............................................175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................
±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Intel is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Functions
Tristate#
FSEL0
0
0
0
1
1
0
1
1
1
0
1
1
FSEL1
x
x
0
0
1
1
CPU
SDRAM
Three-state
Test
100 MHz
100 MHz
133 MHz
100 MHz
Three-state
Test
66 MHz
100 MHz
133 MHz
133 MHz
Block Diagram
Pin Configuration
Note:
1.
Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
[1]
VDDQ3
VDDQ2
CPU2_ITP
PCI0_ICH
XTAL
OSC
PLL REF FREQ
PLL 1
X2
X1
REF0/FSEL1
PCI1:6
USB
DOT
PLL2
VDDQ3
I
2
C
Logic
SDATA
SCLK
3V66_0:1
CPU0:1
FSEL0:1
VDDA
APIC0:1
Divider,
Delay,
and
Phase
Control
Logic
7
2
VDDQ3
2
2
DCLK
SDRAM0:7
8
PWR_DWN#
3V66_AGP
VDDA
Tristate#
*REF0/FSEL1
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
3V66_AGP
VDDQ3
VDDQ3
PCI0_ICH
PCI1
GND
PCI2
PCI3
GND
PCI4
PCI5
PCI6
VDDQ3
VDDA
GNDA
GND
USB
DOT
VDDQ3
FSEL0
W
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
PWR_DWN#
SCLK
SDATA
Tristate#
56
55
54
53
52
51
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49
48
47
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40
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1
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