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| 型號(hào)： | W230 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大小： | 174K |
| 代理商： | W230 |
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Spread Spectrum FTG for VIA K7 Chipset
W230
Cypress Semiconductor Corporation
Document #: 38-07224 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
Single-chip system frequency synthesizer for VIA K7
chipset
Two copies of CPU output
Six copies of PCI output
One 48-MHz output for USB
One 24-MHz or 48-MHz output for SIO
Two buffered reference outputs
Thirteen SDRAM outputs provide support for 3 DIMMs
Supports frequencies up to 200 MHz
I
2
C interface for programming
Power management control inputs
Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew:......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
: .....................................................................
3.3V±5%
Table 1. Mode Input Table
Mode
0
1
I
2
C is a trademark of Phillips Corporation.
Pin 2
CPU_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
CPUT_CS
CPUT0
(MHz)
100.0
100.0
100.0
95.0
133.3
133.3
133.3
102.0
104.0
106.0
107.0
108.0
109.0
110.0
111.0
112.0
PCI 0:5
(MHz)
33.3
33.3
33.3
31.7
33.3
33.3
33.3
34.0
34.6
35.3
35.6
36.0
36.3
36.6
37.0
37.3
Spread
Spectrum
–
0.5%
±0.25%
±0.5%
OFF
–
0.5%
±0.25%
±0.5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
FS3 FS2 FS1 FS0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Block Diagram
Pin Configuration
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
[1]
VDDQ3
REF0/(CPU_STOP#)
REF1/FS0
PCI0/MODE
PCI1/FS1
XTAL
OSC
PLL Ref Freq
PLL 1
X2
X1
VDDQ3
Stop
PCI2
PCI3
PCI4
PCI5
48MHz/FS2
VDDQ3
PLL2
÷
2,3,4
PWRDWN#
VDDQ3
I
2
C
Logic
SCLK
I/O Pin
Control
SDRAM0:12
SDRAMIN
13
CPUT0
CPUC0
÷
2
CPUT_CS
VDDQ3
REF0/(CPU_STOP#)
GND
X1
X2
VDDQ3
PCI0/MODE
PCI1/FS1*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
I
2
C
{
GND
SDATA
SCLK
W
REF1/FS0*
GND
CPUT_CS
GND
CPUC0
CPUT0
VDDQ3
PWRDWN#*
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS2*
24_48MHz/FS3^
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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