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參數(shù)資料
| 型號： | W233 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 178K |
| 代理商： | W233 |
PRELIMINARY
Spread Spectrum FTG for VIA Mobile K7 Chipset
W233
Cypress Semiconductor Corporation
Document #: 38-07250 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
Single-chip system frequency synthesizer for VIA Mo-
bile K7 chipset
Two copies of CPU output
Seven copies of PCI output
One 48-MHz output for USB
One 24-MHz or 48-MHz output for SIO
Three buffered reference outputs
Six SDRAM outputs provide support for three SODIMMs
Supports frequencies up to 166 MHz
SMBus interface for programming
Power management control inputs
Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew:......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DD
: .........................................................................
3.3V±5%
SDRAMIN to SDRAM0:5 Delay:............................2.0 ns typ.
Table 1. Pin Selectable Frequency
Input Address
CPU
(MHz)
133.3
100.0
133.3
100.0
133.3
100.0
133.3
100.0
95.0
102.0
104.0
106.0
108.0
110.0
111.0
112.0
PCI
(MHz)
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
31.7
34.0
34.6
35.3
36.0
36.6
37.0
37.3
Spread
Spectrum
OFF
OFF
±0.5%
±0.5%
–
0.5%
–
0.5%
±0.25%
±0.25%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FS2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Block Diagram
Pin Configuration
[1]
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.
VDD_REF
REF0_2X
REF1
REF2/FS3*
PCI0/FS1
PCI1
OSC
PLL 1
X2
X1
VDD_PCI
PCI_F/FS2
PCI2
PCI3
PCI4
PCI5
PCI6
48MHz/FS0
*SEL24_48#/24_48MHz
VDD_SDRAM
PLL2
÷
2,3,4
CLK_STOP#
VDD_48MHz
SMBus
Logic
SDATA
SCLK
I/O Pin
Control
SDRAM0:5
SDRAMIN
7
CPUT0_F
CPUC0_F
÷
2
CPU_CS
VDD_REF
X1
X2
*FS2/PCI_F
*FS1/PCI0
VDD_PCI
GND_PCI
PCI1
PCI2
PCI3
PCI4
PCI5
GND_PCI
VDD_PCI
PCI6
*SDRAM_STOP#
*PCI_STOP#
SDRAMIN
VDD_CORE
GND_CORE
GND_48MHz
*FS0/48MHz
*SEL24_48#/24_48MHz
VDD_48MHz
W
REF0_2X
REF1
REF2/FS3*
GND_REF
GND_CPU
VDD_CPU
CPU_CS
CPUT0_F
CPUC0_F
CPU_STOP#*
STOP_CLK#*
SDRAM0
SDRAM1
VDD_SDRAM
GND_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
VDD_SDRAM
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CStop
CPU_STOP#
Stop
PCI_STOP#
VDD_CPU
Stop
SDRAM_F
SDRAM_STOP#
CStop
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