
133-MHz Spread Spectrum FTG for
Mobile Pentium III Platforms
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
CPU Output Skew: ......................................................150 ps
3V66 Output Skew: .....................................................175 ps
APIC, SDRAM Output Skew: ......................................250 ps
PCI Output Skew:........................................................500 ps
VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM):.........3.3V±5%
VDDQ2 (CPU, APIC):....... 2.5V±5%in Selectable Frequency
Table 1. Pin Selectable Frequency
Input
Address
Output Frequencies
FS1 FS0 CPU SDRAM 48MHz PCI APIC
0
0
66
100
0
1
100
100
1
0
133
133
1
1
133
100
W254B
Cypress Semiconductor Corporation
Document #: 38-07233 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 22, 2002
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology (–0.5% and ±0.5%)
Single chip system FTG for Mobile Intel
Platforms
Two CPU outputs
Seven copies of PCI clock (one Free Running)
Seven SDRAM clock (one DCLK for Memory Hub)
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video DOT clock
Three 3V66 Hublink/AGP outputs
One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)
One APIC outputs
One buffered reference output
Supports frequencies up to 133 MHz
SMBus interface for programming
Power management control inputs
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
Intel and Pentium are registered trademarks of Intel Corporation.
REF
3V66
48
MHz
33
MHz
14.318
MHz
66
MHz
Block Diagram
Pin Configuration
VDD_48
VDD_REF
X1
X2
GND_REF
GND_PCI
PCI_F/FS0^
PCI1/FS1^
PCI2
PCI3
PCI4
PCI5
PCI6
VDD_3V66
3V66_0
3V66_AGP
GND_3V66
VCH_CLK
GND_48
USB
DOT
GND_CORE
W
REF
APIC
VDD_APIC
VDD_CPU
CPU
CPU_F
GND_CPU
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
DCLK
VDD_SDRAM
CPU_STP#
PCI_STP#
PWR_DWN#
SCLK
SDATA
VDD_CORE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD_REF
REF
VDD_APIC
APIC
CPU
CPU_F
PCI_F/FS0
XTAL
OSC
PLL Ref Freq
X2
X1
VDD_PCI
USB (48MHz)
VCH_CLK
VDD_CPU
SCLK
PCI1/FS1
Stop
CStop
PLL 1
SMBus
Logic
DOT (48MHz)
PLL2
PWR_DWN#
VDD_48
SDATA
VDD_SDRAM
DCLK
SDRAM0:5
VDD_3V66
3V66_0:1
3V66_AGP
Divider
Network
PCI2:6
CPU_STP#
PCI_STP#
3V66_1
VDD_PCI
Note:
1.
Internal pull-down or pull-up resistors present on inputs
marked with * or ^ respectively. Design should not rely solely
on internal pull-up or pull-down resistor to set I/O pins HIGH
or LOW respectively.