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參數資料
| 型號： | W26B02 |
| 英文描述： | SRAM |
| 中文描述： | 靜態存儲器 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 240K |
| 代理商： | W26B02 |
Preliminary W26B02
128K
′
16 CMOS STATIC RAM
Publication Release Date: February 6, 2002
- 1 -
Revision A1
GENERAL DESCRIPTION
The W26B02 is a normal-speed, very low-power CMOS static RAM organized as 131072
×
16 bits that
operates on a wide voltage range from 2.7V to 3.6V power supply. The W26B02, W26B02-LE and
W26B02-LI, can meet the requirement of various operating temperature. This device is manufactured
using Winbond’s high performance CMOS technology.
FEATURES
Low power consumption
Access time: 70 nS
2.7V to 3.6V supply voltage
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 1.5V (min.)
Data byte control
#LB (I/O1
I/O8), #UB (I/O9
I/O16)
Available packages: 44-pin type two TSOP,
and TFBGA
PIN CONFIGURATIONS
48-pin TFBGA TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
44-pin
TSOP
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A10
A11
#OE
#UB
#LB
I/O16
I/O15
I/O14
I/O13
V
SS
NC
44
43
42
41
40
39
38
37
36
A6
A7
A5
A8
A9
35
34
33
I/O10
I/O9
NC
I/O11
I/O12
V
DD
A3
A2
A1
A0
#CS
I/O7
I/O8
#WE
A16
I/O6
I/O5
I/O4
V
DD
V
SS
I/O3
I/O2
I/O1
A12
A4
A14
A13
A15
A
B
C
D
E
F
G
H
1
2
#OE
#UB
3
A0
A3
A5
4
A1
A4
5
A2
#CS
6
NC
NC
A6
A7
A16
A15
A13
A8
I/O5
I/O6
#WE
I/O1
I/O3
I/O2
I/O4
V
SS
V
DD
I/O15
I/O16
V
DD
V
SS
I/O7
I/O8
NC
I/O9
I/O10
A9
A10
A11
A12
NC
NC
A14
I/O11
I/O12
I/O13
I/O14
NC
#LB
BLOCK DIAGRAM
CORE CELL ARRAY
1024 ROWS
128 X 16 COLUMNS
DATA
CLK
R
O
W
D
E
C
O
D
E
R
A6
I/O CKT.
COLUMN DECODER
#WE
#OE
CLK GEN.
PRECHARGE CKT.
A5
A4
A3
A2
A0
A1
#CS
#UB
A16
A15
A14
A13
A12
A10
A8
A7
I/O1
:
I/O16
A9
A11
#LB
PIN DESCRIPTION
SYMBOL
A0
A16
I/O1
I/O16
#CS
#WE
#LB
#UB
#OE
V
DD
V
SS
IC
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select
Write Enable Input
Lower byte select
Upper byte select
Output Enable Input
Power Supply
Ground
Internet Connection
No Connection
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