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參數資料
| 型號： | W3E16M64S-XBX |
| 英文描述： | DDR SDRAM MCP |
| 中文描述： | DDR SDRAM的MCP的 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 416K |
| 代理商： | W3E16M64S-XBX |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W3E16M64S-X BX
November 2003 Rev. 2
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2nprefetch architecture with an
interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the
128MB DDR SDRAM effectively consists of a single 2nbit
wide, one-clock-cycle data tansfer at the internal DRAM core
and two corresponding nbit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along
with data, for use in data capture at the receiver DQS is a
16Mx64 DDR SDRAM
Preliminary*
FEATURES
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High Frequency = 200, 250, 266MHz
Package:
219 Plastic Ball Grid Array (PBGA), 21 x 25mm
2.5V ± 0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture (one
per byte)
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature Ranges
Organized as 16M x 64
Weight: W3E16M64S-XBX - 2 grams typical
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50% SPACE SAVINGS
Reduced part count
Reduced I/O count
17% I/O Reduction
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 64 density (contact factory for
information)
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* This data sheet descrbes a product that is not qualified orcharacterzed and is
subject to change without notice.
GENERAL DESCRIPTION
BENEFITS
21
25
66
TSOP
66
TSOP
66
TSOP
66
TSOP
66
TTSOP
11.9
11.9
11.9
11.9
22.3
Monolithic Solution
Actual Size
W3E16M64S-XBX
S
A
V
I
N
G
S
Area
I/O
Count
4 x 265mm2 = 1060mm2
4 x 66 pins = 264 pins
525mm2
50%
219 Balls
17%
W3E16M64S-XBX
White Electronic Designs
66
TSOP
66
TSOP
66
相關PDF資料 |
PDF描述 |
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| W3E16M72SR-XBX | Registered DDR SDRAM MCP |
| W3E16M72S-XBX | DDR SDRAM MCP |
| W3E232M16S-250STIG | 2x32Mx16bit DDR SDRAM |
| W3E32M64S-200BC | 32Mx64 DDR SDRAM |
| W3E32M64S-200BI | 32Mx64 DDR SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3E16M72S-200BC | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 200 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E16M72S-200BI | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 200 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E16M72S-200BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 DDR SDRAM |
| W3E16M72S-250BC | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E16M72S-250BI | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
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