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參數資料
| 型號： | W3E32M64S-400SBI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM, 0.7 ns, PBGA208 |
| 封裝： | 13 X 22 MM, PLASTIC, BGA-208 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 615K |
| 代理商： | W3E32M64S-400SBI |
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E32M64S-XSBX
November 2005
Rev. 3
32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333**, 400**
Package:
208 Plastic Ball Grid Array (PBGA),
13 x 22mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK
edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRanges
Organized as 32M x 64
Can be user organized as 2x32Mx32 or
4x32Mx16
Weight: W3E32M64S-XSBX — 1.5 grams typical
**
For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature
CL = 3.
* This product is subject to change without notice.
*** For 400Mbs operation at commercial or industrial temperature CL = 3.
*This product is under development, is not qualied or characterized and is subject to
change or cancellation without notice.
BENEFITS
73% Space Savings vs. FPBGA
43% Space Savings vs TSOP
Reduced part count
21% I/O reduction vs TSOP
13% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 64M x 64 density (contact factory
for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
strobe transmitted by the DDR SDRAM during READs and
by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
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| W3E32M64SA-200BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64SA-200BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
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