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參數(shù)資料
| 型號(hào)： | W3E64M72S-333BI |
| 英文描述： | 64Mx72 DDR SDRAM |
| 中文描述： | 64Mx72 DDR內(nèi)存 |
| 文件頁(yè)數(shù)： | 1/19頁(yè) |
| 文件大小： | 686K |
| 代理商： | W3E64M72S-333BI |
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W3E64M72S-XBX
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
June 2005
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
64Mx72 DDR SDRAM
FEATURES
Data rate = 200, 250, 266 and 333Mbs
Package:
219 Plastic Ball Grid Array (PBGA), 25 x 32mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock in puts (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
ar chi ec ure; two data accesses per clock cy cle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
re ceived with data, i.e., source-syn chro nous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRang es
Organized as 64M x 72
Weight: W3E64M72S-XBX - 4.5 grams typical
* This product is under development, is not qualified or characterized and is subject
to change or cancellation without notice.
BENEFITS
66% Space Savings vs. TSOP
Re duced part count
55% I/O reduction vs TSOP
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS,
dy nam c ran dom-access, memory using 9 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 512MB DDR SDRAM uses a double data rate
ar chi ec ure to achieve high-speed operation. The
double data rate ar chi ec ure is essentially a 2n-prefetch
architecture with an in er ace designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two cor e spond ng n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.
The 512MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Com mands (ad dress and control signals) are registered
at every positive edge of CK. Input data is registered on
both edg es of DQS, and out put data is ref er enced to both
edges of DQS, as well as to both edges of CK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3E64M72S-333BM | 64Mx72 DDR SDRAM |
| W3E64M72S-333ESC | 64Mx72 DDR SDRAM |
| W3E64M72S-333ESI | 64Mx72 DDR SDRAM |
| W3E64M72S-333ESM | 64Mx72 DDR SDRAM |
| W3E64M72S-XBX | 64Mx72 DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E64M72S-333BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-333ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-333ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-333ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-333SBI | 制造商:Microsemi Corporation 功能描述:W3E64M72S-333SBI - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
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