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參數(shù)資料
| 型號： | W3EG128M72ETSU-JD3 |
| 英文描述： | 1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| 中文描述： | 1GB的- 128Mx72 DDR SDRAM的無緩沖ECC瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 277K |
| 代理商： | W3EG128M72ETSU-JD3 |
White Electronic Designs
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
January 2005
Rev. 0
W3EG128M72ETSU-D3
-JD3
-AJD3
ADVANCED*
1GB – 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
JEDEC design specification
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply:
V
CC
= V
CCQ
= +2.5V ± 0.2V (100, 133 and
166MHz)
V
CC
= V
CCQ
= +2.6V ± 0.1V (200MHz)
JEDEC standard 184 pin DIMM package
Package height options:
JD3: 30.48 mm (1.20”)
AJD3: 28.70 mm (1.13”)
NOTE: Consult factory for availability of:
Lead-free products
Vendor source control option
Industrial temperature option
DESCRIPTION
The W3EG128M72ETSU is a 128Mx72 Double Data Rate
SDRAM memory module based on 1Gb DDR SDRAM
components. The module consists of nine 128Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same device to
be useful for a variety of high bandwidth, high performance
memory system ap pli ca ions.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
2.5-3-3
DDR400@CL=3
200MHz
3-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
DDR200@CL=2
100MHz
2-2-2
Clock Speed
CL-t
RCD
-t
RP
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