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參數(shù)資料
型號(hào): W3EG6462S263JD3
英文描述: 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED
中文描述: 512MB的- 2x32Mx64 DDR SDRAM內(nèi)存緩沖
文件頁(yè)數(shù): 1/13頁(yè)
文件大小: 250K
代理商: W3EG6462S263JD3
White Electronic Designs
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
ADVANCED*
W3EG6462S-D3
-JD3
May 2005
Rev. 4
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
JEDEC design specified
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
V
CC
= V
CCQ
= +2.5V ±0.2V (100, 133 and 166
MHz)
V
CC
= V
CCQ
= +2.6V ±0.1V (200 MHz)
Standard 184 pin DIMM package
JD3 PCB height: 30.48 (1.20") MAX
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The W3EG6462S is a 2x32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of sixteen 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184 pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
512MB – 2x32Mx64 DDR SDRAM UNBUFFERED
OPERATING FREQUENCIES
DDR333 @CL=2.5
DDR266 @CL=2.5
166MHz
2.5-3-3
DDR400 @CL=3
200MHz
3-3-3
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
Clock Speed
CL-t
RCD
-t
RP
133MHz
2-3-3
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