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參數(shù)資料
型號(hào): W3EG72128S265JD3
英文描述: 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED
中文描述: 1GB的- 2x64Mx72 DDR內(nèi)存緩沖
文件頁(yè)數(shù): 1/12頁(yè)
文件大?。?/td> 245K
代理商: W3EG72128S265JD3
White Electronic Designs
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
May 2005
Rev. 3
W3EG72128S-D3
-JD3
FEATURES
Double-data rate architecture
DDR200, DDR266, DDR333 and DDR400
JEDEC design specifications
BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
V
CC
= V
CCQ
= +2.5V ± 0.20V (100, 133, 166MHz)
V
CC
= V
CCQ
= +2.6V ± 0.10V (200MHz)
JEDEC Standard 184 pin DIMM package
PCB height: 30.48 (1.20")
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
1GB – 2x64Mx72 DDR SDRAM UNBUFFERED
DESCRIPTION
the W3EG72128S is a 2x64Mx72 Double data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 64Mx8
DDR SDRAMs in 66 pin TSOP packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precisse cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR400 @CL=3
200MHz
3-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
Clock Speed
CL-t
RCD
-t
RP
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