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參數資料
| 型號： | W3HG2128M72AEF534F1SBG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數： | 1/18頁 |
| 文件大小： | 348K |
| 代理商： | W3HG2128M72AEF534F1SBG |
W3HG2128M72AEF-Fx
June 2007
Rev. 3
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
2GB – 2x128Mx72 DDR2 SDRAM FBDIMM, ECC
VCC = VCCQ = +1.8V for DDR2 SDRAM
VREF = 0.9V SDRAM C/A termination
VCC = 1.5V for advanced memory buffer (AMB)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual rank
RoHS
DESCRIPTION
The W3HG2128M72AEF is a 2x128Mx72 fully buffered
240-pin Double Data Rate 2 SDRAM memory module
based on 512Mb DDR2 SDRAM components. The module
consists of thirty six 128Mx4, in FBGA package and a AMB
mounted on a 240 pin FR4 substrate.
* This product is under development, is not qualied or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
Vendor source control options
FEATURES
240-pin DDR2 fully buffered, dual in-line memory
module (FBDIMM) with ECC to detect and report
channel errors to the host memory controller.
Fast DDR2 DRAM data transfer rates: PC2-6400*,
PC2-5300, and PC2-4300
3.2 Gb/s and 4.0 Gb link transfer rates
High speed differential point-to-point link between
host memory controller and the AMB using serial,
dual-simplex bit lanes
10-pair southbound (data path to FBDIMM)
14-pair northbound (data path to FBDIMM)
Fault tolerant; can work around a bad bit lane in
each direction
High density scaling with up to 8 dual-rank modules
(288 DDR2 SDRAM devices) per channel
SMBus interface to AMB for conguration register
access.
In-band and out-bank command access
Deterministic protocol
Enables memory controller to optimize DRAM
access for maximum performance
Delivers precise control and repeatable memory
behavior
Automatic DDR2 SDRAM bus and channel
calibration
Transmitter de-emphasis to reduce ISI
MBIST and IBIST test functions
Transparent mode for DDR2 SDRAM test support
PERFORMANCE PARAMETERS
Speed Grade
Module Bandwidth
Peak Channel Throughput
Link Transfer Rate
Latency (CL-tRCD-tRP)
665
PC2-5300
8.0 GB/s
4.0 GT/s
5-5-5
534
PC2-4200
6.4 GB/s
3.2 GT/s
4-4-4
* Consult factory for availability
Note: JEDEC has not yet adopted a nal FBDIMM standard
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