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參數資料
| 型號： | W40S11-23 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Buffer/Driver(時鐘緩沖器/驅動器) |
| 中文描述： | 時鐘緩沖器/驅動器（時鐘緩沖器/驅動器） |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 123K |
| 代理商： | W40S11-23 |
Clock Buffer/Driver
W40S11-23
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
September 28, 1999 rev. **
408-943-2600
Features
Thirteen skew-controlled CMOS clock outputs
(SDRAM0:12)
Supports three SDRAM DIMMs
Ideal for high-performance systems designed around
Intel’s latest chip set
I
2
C serial configuration interface
Clock Skew between any two outputs is less than 250 ps
1- to 5-ns propagation delay
DC to 133-MHz operation
Single 3.3V supply voltage
Low power CMOS design packaged in a 28-pin, 300-mil
SOIC (Small Outline Integrated Circuit)
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output
clock buffer. Output buffer impedance is approximately 15
,
which is ideal for driving SDRAM DIMMs.
Key Specifications
Supply Voltages:........................................... V
DD
= 3.3V±5%
Operating Temperature:.................................... 0°C to +70°C
Input Threshold: ..................................................1.5V typical
Maximum Input Voltage:.......................................V
DD
+ 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:12 Propagation Delay:......1.0 to 5.0 ns
Output Edge Rate:.............................................. >1.5 V/ns
Output Clock Skew:.................................................. ±250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance:...............................................15
typical
Output Type:................................................CMOS rail-to-rail
Pin Configuration
SOIC
Block Diagram
Note:
1.
Internal pull-up resistor of 250K on SDATA and SCLOCK inputs
(not CMOS level).
[1]
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM0
Serial Port
SCLOCK
SDATA
Device Control
BUF_IN
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDATA
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM7
SDRAM6
GND
GND
SCLOCK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
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