
W6692
PCI ISDN S/T-CONTROLLER
Publication Release Date: October 1998
- 1 -
Revision A1
Table of Contents-
1. GENERAL DESCRIPTION............................................................................................................. 5
2. FEATURES.................................................................................................................................... 5
3. PIN CONFIGURATION.................................................................................................................. 6
4. PIN DESCRIPTION........................................................................................................................ 6
5. SYSTEM DIAGRAM AND APPLICATIONS.................................................................................... 9
6. BLOCK DIAGRAM....................................................................................................................... 10
7. FUNCTIONAL DESCRIPTIONS................................................................................................... 11
7.1 Main Block Functions............................................................................................................................11
7.2 Layer 1 Functions Descriptions.............................................................................................................12
7.2.1 S/T Interface Transmitter/Receiver..................................................................................................12
7.2.2 Receiver Clock Recovery And Timing Generation............................................................................15
7.2.3 Layer 1 Activation/Deactivation .......................................................................................................16
7.2.3.1 States Descriptions and Command/Indication Codes................................................................................. 16
7.2.3.2 State Transition Diagrams ........................................................................................................................ 18
7.2.4 D Channel Access Control...............................................................................................................21
7.2.5 Frame Alignment ............................................................................................................................21
7.2.5.1 FAinfA_1fr................................................................................................................................................ 22
7.2.5.2 FAinfB_1fr................................................................................................................................................ 22
7.2.5.3 FAinfD_1fr ............................................................................................................................................... 22
7.2.5.4 FAinfA_kfr................................................................................................................................................ 23
7.2.5.5 FAinfB_kfr................................................................................................................................................ 24
7.2.5.6 FAinfD_kfr ............................................................................................................................................... 24
7.2.5.7 Faregain................................................................................................................................................... 24
7.2.6 Multiframe Synchronization.............................................................................................................25
7.2.7 Test Functions ................................................................................................................................26
7.3 Serial Interface Bus ..............................................................................................................................27
7.4 B Channel Switching.............................................................................................................................28
7.5 PCM Port..............................................................................................................................................28
7.6 D Channel HDLC Controller..................................................................................................................28
7.6.1 D Channel Message Transfer Modes...............................................................................................30
7.6.2 Reception of Frames in D Channel..................................................................................................30
7.6.3 Transmission of Frames in D Channel.............................................................................................31