
W83877AF
Publication Release Date: Dec. 1996
PreliminaryVersion 0.52
- I -
TABLE OF CONTENTS
GENERAL DESCRIPTION...........................................................................................................................1
FEATURES.....................................................................................................................................................2
PIN CONFIGURATION.................................................................................................................................4
1.0 PIN DESCRIPTION................................................................................................................................5
1.1 HOST INTERFACE...........................................................................................................................5
1.2 SERIAL PORT INTERFACE.............................................................................................................6
1.3 GAME PORT/POWER DOWN INTERFACE....................................................................................8
1.4 MULTI-MODE PARALLEL PORT....................................................................................................9
1.5 IDE AND FDC INTERFACE...........................................................................................................17
2.0 FDC FUNCTIONAL DESCRIPTION...................................................................................................19
2.1 W83877AF FDC...............................................................................................................................19
2.2 REGISTER DESCRIPTIONS...........................................................................................................33
3.0 IDE..........................................................................................................................................................45
3.1 IDE DECODE DESCRIPTION ........................................................................................................45
4.0 UART PORT..........................................................................................................................................45
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)....................45
4.2 REGISTER ADDRESS.....................................................................................................................45
4.3 IR PORT...........................................................................................................................................52
5.0 PARALLEL PORT...............................................................................................................................86
5.1 PRINTER INTERFACE LOGIC.......................................................................................................86
5.2 ENHANCED PARALLEL PORT (EPP)...........................................................................................88
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT.................................................................92
5.4 EXTENSION FDD MODE (EXTFDD)..........................................................................................101
5.5 EXTENSION 2FDD MODE (EXT2FDD) ......................................................................................101
5.6 EXTENSION ADAPTER MODE (EXTADP) (PATENT PENDING).............................................102
5.7 JOYSTICK MODE (PATENT PENDING).....................................................................................102
6.0 GAME PORT DECODER...................................................................................................................103
7.0 PLUG AND PLAY CONFIGURATION.............................................................................................103