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參數資料
| 型號： | W93902 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 尋呼電路 |
| 英文描述： | POCSAG Decoder For Pagers(尋呼機的POCSAG 解碼器) |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數： | 1/22頁 |
| 文件大小： | 244K |
| 代理商： | W93902 |
W93902
POCSAG DECODER FOR PAGERS
Publication Release Date: October 1997
- 1 -
Revision A3
GENERAL DESCRIPTION
The W93902 is a very-low-power decoder for pagers that is fully compatible with CCIR Radio Paging
Code Number 1 (POCSAG code) operating at 512, 1200, or 2400 bps using a single 76.8 KHz crystal.
To enhance the sensitivity of the pager system, a digital filter and digital PLL have been incorporated
to remove the noise factor generated by the RF part and lock the signal phase.
To reduce the RF turn-on time and minimize power consumption, an advanced synchronization
algorithm (1/18 turn on-time, as opposed to 1/17 or 1/16) is used to provide synchronization.
Synchronization skip mode is also available for power reduction.
For convenient pager programming, the decoder provides fully software-programmable options and a
simple CPU control format (data output packaged as 4/7/8 bits or not packaged). Also included are
independent buzzer and LED frequency control outputs and a reference clock (32768 Hz, 64 Hz, 16
Hz, 1/60 Hz) that can be output or disabled. The decoder supports four independent user addresses,
which can be assigned to different frames.
FEATURES
Data rate of 512, 1200, or 2400 bps
32768 Hz or 76800 Hz crystal
Embedded digital filter and digital PLL
Real two-random-bit error correction or one-bit error correction ability, plus four-bit burst error
correction can be selected
1/18 RF enable time (more efficent than 1/17 or 1/16)
Four real independent user address in different frames
25% to 75% duty cycle data capability in receive mode
2.7/3.2/2/4 KHz frequency output controlled by two pins, FBUZ1 and FBUZ2
6-bit/8-bit preamble acknowledge selection
Four preamble search delay time settings
Selection of from 1 to 15 sync search retry attempts
Multi-frequency output for LED or other usage
Inversion or non-inversion NRZIN signal and BS1/BS2/BS3 selection
4/7/8 bits package per byte output selection for receiving messages
Independent power-saving control pin allows device to enter or exit reception mode at any time
16 selections for RF and PLL stable time
Five selections for out-of-range indication
Two selections for end-of-message condition
Embedded power-on reset circuit
Four Rxclk rate selection
2.5 to 5V operating voltage range
Packaged in small size 24-pin SSOP
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W93910 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ERMES PAGING DECODER |
| W9393 | 制造商:Winslow Adaptics Ltd 功能描述:28/32 way DIL-PLCC plug conversion,W9393 |
| W9395 | 制造商:Winslow Adaptics Ltd 功能描述:40/44 way DIL-PLCC plug conversion,W9395 |
| W93-A112-50 | 制造商:TE Connectivity 功能描述: |
| W93A8AD/SYC/H | 制造商:Kingbright Corporation 功能描述: |
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