- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄361798 > W981204AH-8H x4 SDRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | W981204AH-8H |
| 英文描述： | x4 SDRAM |
| 中文描述： | x4內(nèi)存 |
| 文件頁(yè)數(shù)： | 1/42頁(yè) |
| 文件大小： | 1082K |
| 代理商： | W981204AH-8H |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)
W981204AH
8M x 4 Banks x 4 bits SDRAM
Revision 1.0 Publication Release Date: June, 2000
- 1 -
Features
3.3V
±
0.3V power supply
Up to 133 MHz clock frequency
8,388,608 words x 4 banks x 4 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst read, Single Writes Mode
Byte data controlled by DQM
Power-Down Mode
Auto-Precharge and controlled precharge
4K refresh cycles / 64ms
Interface: LVTTL
Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W981204AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 8M words x 4 banks
x 4 bits. Using pipelined architecture and 0.20um process technology, W981204AH delivers a data bandwidth of up to 133M
(-75) words per second. To fully comply with the personal computer industrial standard, W981204AH is sorted into two speed
grades: -75 and -8H. The -75 is compliant to the PC133/CL3 specification. The -8H is compliant to the PC100/CL2
specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically
generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at
each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential
burst to maximize its performance. W981204AH is ideal for main memory in high performance applications.
Key Parameters
Symbol
t
CK
Clock Cycle Time
t
AC
Access Time from CLK
t
RP
Precharge to Active Command
t
RCD
Active to Read/Write Command
I
CC1
Operation Current ( Single bank )
I
CC4
Burst Operation Current
I
CC6
Self-Refresh Current
Description
min/max
min
max
min
min
max
max
max
-75 (PC133) -8H (PC100)
7.5ns
5.4ns
20ns
20ns
85mA
120mA
2mA
8ns
6ns
20ns
20ns
80mA
110mA
2mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W982504AH-7 | x4 SDRAM |
| W982504AH-75 | x4 SDRAM |
| W982504AH-8H | x4 SDRAM |
| W982508AH-7 | x8 SDRAM |
| W982508AH-75 | x8 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W981208AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 8 bit x 4 Banks SDRAM |
| W981208AH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W981208AH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W981208BH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 8 BIT SDRAM |
| W981208BH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。