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參數(shù)資料
| 型號： | W982516AH-7 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 1/41頁 |
| 文件大小： | 1369K |
| 代理商： | W982516AH-7 |
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W982504AH
16M
′
4 BANKS
′
4 BIT SDRAM
Publication Release Date: December 2000
- 1 -
Revision A2
GENERAL DESCRIPTION
W982504AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
16M words
×
4 banks
×
4 bits. Using pipelined architecture and 0.175
μ
m process technology,
W982504AH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W982504AH is sorted into three speed grades: -7, -75 and -
8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the
PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W982504AH is ideal for main memory in
high performance applications.
FEATURES
3.3V
±
0.3V Power Supply
Up to 143 MHz Clock Frequency
16,777,216 Words
×
4 banks
×
4 bits organization
Auto Refresh and Self Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Power-down Mode
Auto-Precharge and Controlled Precharge
4K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil - 0.80
KEY PARAMETERS
SYM.
DESCRIPTION
MIN.
/MAX.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
-7
(PC133, CL2)
7 nS
5.4 nS
15 nS
15 nS
80 mA
100 mA
3 mA
-75
(PC133, CL3)
7.5 nS
5.4 nS
20 nS
20 nS
75 mA
95 mA
3 mA
-8H
(PC100)
8 nS
6 nS
20 nS
20 nS
70 mA
90 mA
3 mA
t
CK
t
AC
t
RP
t
RCD
I
CC1
I
CC4
I
CC6
Clock Cycle Time
Access Time from CLK
Precharge to Active Command
Active to Read/Write Command
Operation Current (Single bank)
Burst Operation Current
Self-Refresh Current
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W982516AH-75 | x16 SDRAM |
| W982516AH-8H | x16 SDRAM |
| W986432DH-5 | SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W986432DH-6 | SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W986432DH-6I | SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W982516AH-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| W982516AH75L | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 16BIT SDRAM |
| W982516AH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 16BIT SDRAM |
| W982516BH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M X 4 BANKS X 16 BIT SDRAM |
| W982516BH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M X 4 BANKS X 16 BIT SDRAM |
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