
W987Z6CBN/BG
2M
×
4 BANKS
×
16 BIT SDRAM
Publication Release Date: March 2002
- 1 -
Revision P11
GENERAL DESCRIPTION
W987Z6CB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words
×
4 banks
×
16 bits. Using pipelined architecture and 0.175
μ
m process technology,
W987Z6CB delivers a data bandwidth of up to 125M words per second (-8). For different application,
W987Z6CB is sorted into two speed grades: -75 and –8. The –75 is compliant to the 133MHz/CL3
specification; the -8 is compliant to the 125Mhz/CL3 specification. For handheld device application,
these parts are specially designed with several power saving mechanisms to achieve extremely low
Self Refresh Current.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W987Z6CB is ideal for main memory in
high performance applications.
FEATURES
Power supply V
DD
= 2.7V
3.6V
V
DD
Q = 2.7V
3.6V
Standard Self Refresh Mode
Power Down Mode
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
4K Refresh cycles / 64 mS
Interface: LVTTL
Package: 54 balls FBGA,
Operating Temperature Range
Commercial temperature(0
°
C
70
°
C)
Industrial temperature(-4
0
°
C
85
°
C)
AVAILABLE PART NUMBER
Part Number
Speed
Self Refresh
Current (max.)
Temperature
Range
0
°
C
70
°
C
Lead-free
Package
W987Z6CBN75
133MHz/CL3
400
μ
A
No
W987Z6CBG75
133MHz/CL3
400
μ
A
400
μ
A
400
μ
A
0
°
C
70
°
C
0
°
C
70
°
C
0
°
C
70
°
C
Yes
W987Z6CBN80
125MHz/CL3
No
W987Z6CBG80
125MHz/CL3
Yes