
32K x 8 3.3V Static RAM
WCFS0808V1E
Document #: 38-05225 Rev. **
Revised February 11, 2002
1WCFS0808V1E
Features
Single 3.3V power supply
Ideal for low-voltage cache memory applications
High speed
—12/15 ns
Plastic SOJ and TSOP packaging
Functional Description
The WCFS0808V1E is a high-performance 3.3V CMOS Static
RAM organized as 32K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE) and ac-
tive LOW Output Enable (OE) and three-state drivers. The de-
vice has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The WCFS0808V1E is available in 28-pin stan-
dard 300-mil-wide SOJ and TSOP Type I packages.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
WE
A
4
A
3
A
2
A
1
OE
A
0
V
CC
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
5
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
32K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
Selection Guide
WCFS0808V1E 12ns
12
55
500
WCFS0808V1E 15ns
15
50
500
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (
μ
A)