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參數資料
| 型號： | WCMA4016U1X |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256K x 16 Static RAM |
| 中文描述： | 256K × 16靜態RAM |
| 文件頁數： | 1/9頁 |
| 文件大小： | 164K |
| 代理商： | WCMA4016U1X |
256K x 16 Static RAM
WCMA4016U1X
Weida Semiconductor, Inc.
Y62147BV
L
Features
Low voltage range: 2.7V–3.6V
Ultra-low active, standby power
Easy memory expansion with CE
1
and CE
2
and OE fea-
tures
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
[1]
The WCMA4016U1X is a high-performance CMOS static
RAM organized as 262,144 words by 16 bits. This device
features advanced circuit design to provide ultra-low active
current and standby current. This is ideal for providing more
battery life in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99% when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
18
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table at the back of this
datasheet for a complete description of read and write modes.
.
Logic Block Diagram
Pin Configurations
I/O
0
– I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
I/O
8
– I/O
15
A
1
A
1
A
0
A
1
A
9
Power
-
Down
Circuit
BHE
BLE
WE
V
CC
A
11
A
10
NC
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
FBGA (Top View)
256K × 16
RAM Array
2048 × 2048
WE
BLE
BHE
CE
2
CE
1
OE
CE
2
CE
1
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相關代理商/技術參數 |
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|---|---|
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