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參數(shù)資料
| 型號： | WED2DL36513AV25 |
| 英文描述： | 512Kx36 Synchronous Pipeline Burst SRAM(高速低功耗CMOS，2.5ns,512Kx36 同步流水線脈沖靜態(tài)RAM) |
| 中文描述： | 512Kx36同步管道爆裂的SRAM（高速低功耗的CMOS，2.5ns，512Kx36同步流水線脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 266K |
| 代理商： | WED2DL36513AV25 |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL36513V
WED2DL36513AV
October 1999 Rev. 2
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced
CMOS process. WEDC’s 16Mb SyncBurst SRAMs integrate two
512K x 18 SRAMs into a single BGA package to provide 512K x
36 configuration. All synchronous inputs pass through registers
controlled by a positive - edge-triggered single-clock input (CLK).
The synchronous inputs include all addresses, all data inputs,
active LOW chip enable (CE), burst control inputs (ADSC, ADSP,
ADV), byte write enables (BW
0-3
) and global write (GW). Asyn-
chronous inputs include the output enable (OE), clock (CLK) and
snooze enable (ZZ). There is also a burst mode input (MODE) that
selects between interleaved and linear burst modes. Write Cycles
can be from one to four bytes wide, as controlled by the write
control inputs. Burst operation can be initiated with either address
status processor (ADSP) or address status controller (ADSC)
inputs. Subsequent burst addresses can be internally generated
as controlled by the burst advance input (ADV).
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
512Kx36 Synchronous Pipeline Burst SRAM
PRELIMINARY*
FEATURES
I
Fast clock speed: 200, 166, 150 & 133MHz
I
Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
I
Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
I
Available with 1.5ns setup and 0.5ns hold times or 1.0ns setup
and hold times.
I
Single +3.3V power supply (V
DD
)
I
Seperate +3.3V or +2.5V isolated output buffer supply (V
DDQ
)
I
Snooze Mode for reduced-power standby
I
Single-cycle deselect
I
Common data inputs and data outputs
I
Individual Byte Write control and Globa Write
I
Clock-controlled and registered addresses, data I/Os and
control signals
I
Burst control (interleaved or linear burst)
I
Packaging:
119-bump BGA package
I
Low capacitive bus loading
I
Available in either single CE or three CE configuration
I
IEEE 1149.1 JTAG Compatible Boundary Scan (available on
single CE version only)
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
SA
SA
SA
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
SA
NC
TMD
SA
SA
SA
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
MODE
SA
TDI
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
SA1
SA0
V
DD
SA
TCK
SA
SA
SA
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
SA
TDO
SA
SA
SA
DQP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
SA
NC
NC
V
DDQ
NC
NC/CE
2
*
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC/CE
2
*
ZZ
V
DDQ
DQ
b
,
DQP
b
DQ
a
,
DQP
a
GW
ADV
SA
CLK
ADSP
ADSC
OE
BWE
CE
MODE
ZZ
BW
a
BW
b
512K x 18
SSRAM
DQ
d
,
DQP
d
DQ
c
,
DQP
c
512K x 18
SSRAM
BW
c
BW
d
* Enable on pins C7 and R7 are options for the three CE density only.
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