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參數(shù)資料
| 型號(hào)： | WED2ZL362MSJ30BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 2M X 36 MULTI DEVICE SRAM MODULE, 3 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 270K |
| 代理商： | WED2ZL362MSJ30BC |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED2ZL362MSJ
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDCs 72Mb
SyncBurst SRAMs integrate two 2M x 18 SRAMs into a
single BGA package to provide a 2M x 36 configuration.
All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single-clock input
(CLK). The NBL or No Bus Latency Memory utilizes all
the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except
output enable and linear burst order are synchronized
to input clock. Burst order control must be tied High or
Low. Asynchronous inputs include the sleep mode en-
able (ZZ) and Output Enable (OE). Write cycles are in-
ternally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip
write pulse generation and provides increased timing
flexibility for incoming signals.
72Mb, 2M x 36 Synchronous Pipeline Burst NBL SRAM
FIG. 1 PIN CONFIGURATION
BLOCK DIAGRAM
(TOP VIEW)
Address Bus
(SA0 SA20)
DQA, DQB
DQPA, DQPB
DQC, DQD
DQPC, DQPD
DQA DQD
DQPA DQPD
2M x 18
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CE1
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
ZZ
BW
D
BW
A
BW
C
BW
B
FEATURES
n Fast clock speed: 225, 200, 166 and 150MHz
n Fast access times: 2.8, 3.0, 3.5 and 3.8ns
n Fast OE access times: 2.8, 3.0, 3.5 and 3.8ns
n Separate Core and I/O Power Supply
n Snooze Mode for reduced-standby power
n Individual Byte Write control
n Clock-controlled and registered addresses, data I/Os
and control signals
n Burst control (interleaved or linear burst)
n Packaging:
119-bump BGA package, JEDEC Pin Definition
n Low capacitive bus loading
July 2002 Rev 0
ECO # 15239
1
2
3456
7
A
VDDQ
SA
VDDQ
B
NC
CE2
SA
ADV
SA
CE2
NC
C
NC
SA
VDD
SA
NC
D
DQC
DQPC
VSS
NC
VSS
DQPB
DQB
E
DQC
VSS
CE1
VSS
DQB
F
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
G
DQC
BWC
SA
BWB
DQB
H
DQC
VSS
WE
VSS
DQB
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQD
VSS
CLK
VSS
DQA
L
DQD
BWD
NC
BWA
DQA
M
VDDQ
DQD
VSS
CKE
VSS
DQA
VDDQ
N
DQD
VSS
SA1
VSS
DQA
P
DQD
DQPD
VSS
SA0
VSS
DQPA
DQA
R
NC
SA
LBO
VDD
NC
SA
NC
T
NC
SA
ZZ
U
VDDQ
RFU
NC
VDDQ
Advanced
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